1. Field of the Invention
The present invention relates generally to devices that receive and store data for purposes of analysis. More preferably, the present invention relates to a logic device which is capable of receiving test or state data, and which stores that data in a memory device. Still, more particularly, the invention relates to a logic analyzer, which is capable of storing data on-chip with a timestamp that indicates the timing of the saved data relative to other stored data.
2. Background of the Invention
Data in a computer system can be obtained in two basic ways. First, the data can be routed to a requesting device or an intended target as soon as the data is generated. Second, the data can be stored in memory, and then later retrieved by the requesting device or intended target. The ability to store data in memory increases the efficiency of computer systems because it permits devices to operate independently and to schedule the routing of data using predefined arbitration schemes. One potential downside to this storing and routing of data is that timing information regarding the generation of the data may be lost. While many applications are indifferent to the time when the data was generated, there are certain applications where the timing of data may be critical.
One example where the relative timing of data is critical is during a debug or test operation, when an integrated circuit and/or associated software are tested for efficiency and errors. In these operations, data stored in memory indicates the internal state of the integrated circuit and/or the address of fetched or executed software instructions. The relative timing of this saved data may be critical in reconstructing the operation of the circuit and/or software. Thus, in these and other similar applications, the normal paradigm of generating data, saving data, and retrieving data may cause valuable information regarding the timing of the data to be irretrievably lost.
The testing and debugging of complex integrated circuits normally is performed using expensive external logic analyzers that connect to the external terminals of the integrated circuit. To capture the timing of the data, these external logic analyzers are capable of adding a timestamp to each piece of data that is stored in memory. Because of the very high clock frequencies at which modern integrated circuits operate, these external logic analyzers require a very large timestamp field to identify the timing of the data with the requisite precision. Currently available logic analyzers may use 50 or more bits to encode the relevant timing information. The use of such a large number of bits (or wide value) to encode the timing information can be accomplished because these external logic analyzers usually have access to large memory systems.
The use of external logic analyzers to test and debug an integrated circuit (or group of circuits) suffers in several respects. First, the signals obtained from the external output terminals may require that internal state data be inferred. Second, routing the desired state to external terminals often requires more wiring, silicon, drivers, pads and power than is affordable. Attempts to do so can compromise the normal functioning of the chip. And costs escalate throughout the design, often impacting the micropackaging and system board as well as the die. Third, oftentimes the internal clock rate of the chip operates at a much higher rate than the external logic analyzers that receive and process the data. As an example, processor designs currently under development operate at clock speeds up to and exceeding 2.0 GHz. The fastest commercial logic analyzers are incapable of operating at GHz frequencies. Thus, either certain data must be ignored, or some other mechanism must be employed to capture the high-speed data being generated on the chip. The typical approach is to run the chip at a slower clock speed so the data can be captured by external test equipment. This solution, however, makes it more difficult to detect errors that may only occur when the chip is running at higher clock speeds. Some errors that occur at full clock speed will not exist when the clock speed is slowed to accommodate the off-chip logic analyzers.
As an alternative to sending data off-chip, attempts have been made to capture certain state data on chip, thereby reducing the problems encountered when interfacing slower speed test equipment with high-speed devices. In this approach, an on-chip logic analyzer (OCLA) is provided to acquire and store data on the chip itself In the past, to the extent that designers sought to incorporate memory onto the chip for debug and test purposes, dedicated memory devices (usually RAM) were used. The problem with this approach, however, is that it requires the allocation of a significant amount of chip space to incorporate such a dedicated memory device. While such a dedicated memory device may prove useful during the design and development phase of the chip, it adds little or nothing to the performance of the chip. Thus, the inclusion of dedicated memory space on the chip represents an opportunity cost, and means that functionality and/or performance is sacrificed. Consequently, the inclusion of memory for debug purposes is generally viewed as undesirable because of the attendant loss of performance and functionality that results. If a dedicated memory device is included on the chip, system designers normally require that such a memory be very small in size to minimize the performance and functionality repercussion. As the size of the dedicated memory becomes smaller, so too does the likelihood that sufficient relevant data will be captured to provide an adequate insight into the source of the error.
In assignee's co-pending application entitled Method And Apparatus For Efficiently Implementing Trace And/Or Logic Analysis Mechanisms On A Processor Chip, (Invention Disclosure P01-3848), the teachings of which are incorporated herein, the on-chip cache memory is used to store data from the on-chip logic analyzer. The use of the on-chip cache memory as a storage device for the in-chip logic analyzer permits the storage of a relatively large amount of state data on the chip as compared to previous designs. While the use of the on-chip cache memory greatly expands the amount of state data that can be stored on-chip, the extent of data that can be stored is not limitless. For a processor operating at 2 GHZ, the amount of data that can be stored in a 256 kbyte cache represents only a few microseconds of data. Consequently, if the OCLA stores all incoming internal state data in the cache, the cache would quickly overflow, and potentially relevant data would be overwritten, or ignored. Assignee's co-pending application entitled An Efficient Word Recognizer For A Logic Analyzer, (Invention Disclosure P01-3850) discloses a technique for starting and stopping the storage of internal state data based on user programmed conditions, which can be implemented in an on-chip logic analyzer without consuming a large amount of space or processing power.
The ability to start and stop the storage of state or test data is an extremely powerful tool to the debugger because it permits the most pertinent data to be saved for later analysis. The ability to start and stop data storage, however, has a potential downside. The downside is that the data entries may be stored in a non-linear and unpredictable fashion over a relatively large period of time. As noted in the beginning of this Background section, knowledge of the time relationship of the stored data may be critical to the debug process. To make sense of the stored data, information regarding the timing of the saved data is required. Because of the high clock frequencies of modem integrated circuit designs, very high-resolution, and thus very wide, timestamps are required. A processor with a 1 GHz clock frequency (which is relatively slow by today's standards) must have a 20-bit wide timestamp to provide cycle-by-cycle encoding of a 1 millisecond time span. The problem, in a nutshell, is that providing a high-resolution timestamp requires a large number of bits to encode. In instances where the data storage device is limited in size, the inclusion of timestamps may unduly cramp the amount of memory that can be used for storing test data.
It would be desirable if a timestamp system and technique could be developed which would permit the inclusion of relatively high-resolution timestamp information with the test data, without requiring the use of a large number of data bits to encode the timestamp. Such a technique would be extremely valuable to the debugger, because it would permit a greater quantity of data to be stored at clock frequencies, while still providing critical timing information. Despite the apparent advantages that such a system would offer, to date no such system has been introduced.